Single level metal memory cell using chalcogenide cladding

ABSTRACT

An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to programmable memory devices.

2. Background

Typical memory applications include dynamic random access memory (DRAM),static random access memory (SRAM), erasable programmable read onlymemory (EPROM), and electrically erasable programmable read only memory(EEPROM).

Solid state memory devices typically employ micro-electronic circuitelements for each memory bit (e.g., one to four transistors per bit) inmemory applications. Since one or more electronic circuit elements arerequired for each memory bit, these devices may consume considerablechip “real estate” to store a bit of information, which limits thedensity of a memory chip. The primary “non-volatile” memory element ofthese devices, such as an EEPROM, typically employ a floating gate fieldeffect transistor device that has limited re-programmability and whichholds a charge on the gate of field effect transistor to store eachmemory bit. These classes of memory devices are also relatively slow toprogram.

Phase change memory devices use phase change materials, i.e., materialsthat can be electrically switched between a generally amorphous and agenerally crystalline state, for electronic memory application. One typeof memory element originally developed by Energy Conversion Devices,Inc. of Troy, Mich. utilizes a phase change material that can be, in oneapplication, electrically switched between a structural state ofgenerally amorphous and generally crystalline local order or betweendifferent detectable states of local order across the entire spectrumbetween completely amorphous and completely crystalline states. Typicalmaterials suitable for such application include those utilizing variouschalcogenide elements. These electrical memory devices typically do notuse field effect transistor devices, but comprise, in the electricalcontext, a monolithic body of thin film chalcogenide material. As aresult, very little chip real estate is required to store a bit ofinformation, thereby providing for inherently high density memory chips.The state change materials are also truly non-volatile in that, when setin either a crystalline, semi-crystalline, amorphous, or semi-amorphousstate representing a resistance value, that value is retained untilreset as that value represents a physical state of the material (e.g.,crystalline or amorphous). Thus, phase change memory materials representa significant improvement in non-volatile memory.

One characteristic of memory devices is the need for addressing lines,such as column and row lines to program and read a memory device. Incurrently conceived phase change memory devices a column line and a rowline address a distinct cell formed over a substrate. The EnergyConversion Devices, Inc. structure comprises a double level metal cellstructure with the memory element constituting a cell composed of avolume of memory material, an electrode between a row line and thememory material, and an upper electrode overlying the memory material.The cell is coupled to a column line by a via. The via-column linecontact requires the cell size of the memory device to be increased tosupport the contact pitch. It would be desirable in terms of reducingfabrication complexity, cost, and memory cell size to modify theaddressing line configuration of a memory cell device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an array of memory elements accordingto an embodiment of the invention.

FIG. 2 schematically illustrates a cross-sectional planar side view of aportion of a semiconductor substrate having dielectric trenches formedtherein defining a z-direction thickness of a memory cell in accordancewith one embodiment of the invention of forming a memory element on asubstrate.

FIG. 3 shows the structure of FIG. 2, through the same cross-sectionalview, after the introduction of dopants to form an isolation device fora memory element in accordance with one embodiment of the invention.

FIG. 4 shows the structure of FIG. 3 after the introduction of a maskingmaterial over the structure in accordance with one embodiment of theinvention.

FIG. 5 shows a schematic top view of the structure of FIG. 4.

FIG. 6 shows the cross-section of the structure of FIG. 4 through lineB-B′.

FIG. 7 shows the structure of FIG. 5, through the same cross-sectionalview, after the patterning of the x-direction thickness of a memorycell, the introduction of a dopant between the cells, and theintroduction of a dielectric material over the structure.

FIG. 8 shows the structure of FIG. 7, through the same cross-sectionalview, after the formation of trenches through the dielectric material inaccordance with one embodiment of the invention.

FIG. 9 shows the structure of FIG. 8, through the same cross-sectionalview, after the introduction of an electrode material over the structurein accordance with one embodiment of the invention.

FIG. 10 shows the structure of FIG. 9, through the same cross-sectionalview, after the introduction of a dopant into the electrode material inaccordance with one embodiment of the invention.

FIG. 11 shows the structure of FIG. 10, through the same cross-sectionalview, after the introduction of a modifying species into a portion ofthe electrode material in accordance with one embodiment of theinvention.

FIG. 12 shows the structure of FIG. 11, through the same cross-sectionalview, after the introduction of barrier material over the electrode inaccordance with one embodiment of the invention.

FIG. 13 shows the structure of FIG. 12, through the same cross-sectionalview, after the conformal introduction of a volume of memory materialand barrier materials over the structure, in accordance with oneembodiment of the invention.

FIG. 14 shows the structure of FIG. 13 after the conformal introductionof second conductor or signal line material over the structure inaccordance with an embodiment of the invention.

FIG. 15 shows the structure of FIG. 14 after patterning the secondconductor or signal line material and the memory material intocontiguous strips in accordance with an embodiment of the invention.

FIG. 16 shows a schematic top view of the structure of FIG. 15.

FIG. 17 shows the structure of FIG. 15, through the same cross-sectionalview, after the introduction of the dielectric material over the secondconductor and a third conductor coupled to the first conductor inaccordance with an embodiment of the invention.

FIG. 18 shows a top perspective view of the structure of FIG. 17 withoutdielectric material in accordance with an embodiment of the invention.

FIG. 19 shows a graphical representation of setting and resetting avolume of a phase change memory material in terms of temperature andtime.

DETAILED DESCRIPTION OF THE INVENTION

The invention generally relates to an apparatus used, in one aspect, asa memory structure. In one embodiment, the apparatus includes a volumeof phase change material disposed between a first conductor or signalline and a second conductor or signal line on a substrate, and aplurality of electrodes coupled to the volume of phase change materialand the first conductor or signal line. In one aspect, the phase changematerial is contiguous with the second conductor. In memory deviceapplications, the phase change or memory material is not confined tocellular units. In terms of addressing lines, the second conductor orsignal line and the phase change material may be directly adjacent orelectrically coupled such that via coupling may be eliminated. In thismanner, memory device size can be reduced over prior art structures.

The invention also relates to a method, including a method ofintroducing, over a first conductor or signal line on a substrate, aplurality of electrodes coupled to the first conductor or signal line;introducing a phase change material over the plurality of electrodes andin electrical communication with the plurality of electrodes; andintroducing a second conductor or signal over the phase change materialand coupled to the phase change material. Like the apparatus describedabove, the method includes a method of forming a memory device (or anarray of memory devices). The method simplifies prior art fabricationtechniques by eliminating alignment issues of addressing line to memorymaterial and via to addressing line. The method also eliminated priorart sizing constraints imposed by an overlying via coupling to addressthe memory material.

In the following paragraphs and in association with the accompanyingfigures, an example of a memory device formed according to an embodimentof the invention is presented. The embodiment describes a memorymaterial including a phase change material wherein the phase of thematerial determines the state of the memory element.

FIG. 1 shows a schematic diagram of an embodiment of a memory arraycomprised of a plurality of memory elements presented and formed in thecontext of the invention. In this example, the circuit of memory array 5includes an xy grid with memory element 30 electrically interconnectedin series with isolation device 25 on a portion of a chip. Address lines10 (e.g., columns) and 20 (e.g., rows) are connected, in one embodiment,to external addressing circuitry in a manner known to those skilled inthe art. One purpose of the xy grid array of memory elements incombination with isolation devices is to enable each discrete memoryelement to be read and written without interfering with the informationstored in adjacent or remote memory elements of the array.

A memory array such as memory array 5 may be formed in a portion,including the entire portion, of a substrate. A typical substrateincludes a semiconductor substrate such as a silicon substrate. Othersubstrates including, but not limited to, substrates that containceramic material, organic material, or glass material as part of theinfrastructure are also suitable. In the case of a silicon semiconductorsubstrate, memory array 5 may be fabricated over an area of thesubstrate at the wafer level and then the wafer reduced throughsingulation into discrete die or chips, some or all of the die or chipshaving a memory array formed thereon. Additional addressing circuitry(e.g., decoders, etc.) may be formed in a similar fashion as known tothose of skill in the art.

FIGS. 2-18 illustrate the fabrication of representative memory element15 of FIG. 1. FIG. 2 shows a portion of substrate 100 that is, forexample, a semiconductor substrate. In this example, a P-type dopantsuch as boron is introduced in portion 110. In one example, a suitableconcentration of P-type dopant is on the order of above 5×10¹⁹−1×10²⁰atoms per cubic centimeters (atoms/cm³) rendering portion 110 ofsubstrate 100 representatively P⁺⁺. Overlying portion 110 of substrate100, in this example, is portion 120 of P-type epitaxial silicon. In oneexample, the dopant concentration is on the order of about 10¹⁶−10¹⁷atoms/cm³. The introduction and formation of P-type epitaxial siliconportion 120 and P⁺⁺ silicon portion 110 may follow techniques known tothose of skill in the art.

FIG. 2 also shows shallow trench isolation (STI) structures 130 formedin epitaxial portion 120 of substrate 100. As will become apparent inthe subsequent discussion, STI structures 130 serve, in one aspect, todefine the z-direction thickness of a memory element cell, with at thispoint only the z-direction thickness of a memory element cell defined.In another aspect, STI structures 130 serve to isolate individual memoryelements from one another as well as associated circuit elements (e.g.,transistor devices) formed in and on the substrate. STI structures 130are formed according to techniques known to those skilled in the art.

FIG. 3 shows the structure of FIG. 2 after a further fabricationoperation in memory cell regions 135A and 135B. In one embodiment,memory cell regions 135A and 135B are introduced as strips with thex-direction dimension greater than the z-direction dimension. Overlyingepitaxial portion 120 of substrate 100 is first conductor or signal linematerial 140. In one example, first conductor or signal line material140 is N-type doped polysilicon formed by the introduction of, forexample, phosphorous or arsenic to a concentration on the order of about10¹⁸−10¹⁹ atoms/cm³ (e.g., N⁺ silicon). In this example, first conductoror signal line material 140 serves as an address line, a row line (e.g.,row line 20 of FIG. 1). Overlying first conductor or signal linematerial 140 is an isolation device (e.g., isolation device 25 of FIG.1). In one example, the isolation device is a PN diode formed of N-typesilicon portion 150 (dopant concentration on the order of about10¹⁷−10¹⁸ atoms/cm³) and P-type silicon portion 160 (dopantconcentration on the order of about 10¹⁹−10²⁰ atoms/cm³). Although a PNdiode is shown, it is to be appreciated that other isolation structuresare similarly suitable. Such devices include, but are not limited to,MOS devices.

Referring to FIG. 3, overlying the isolation device in memory cellregions 135A and 135B is reducer material 170 of, in this example, arefractory metal silicide such as cobalt silicide (CoSi₂). Reducermaterial 170, in one aspect, serves as a low resistance material in thefabrication of peripheral circuitry (e.g., addressing circuitry) of thecircuit structure on the chip. Thus, reducer material 170 is notrequired in terms of forming a memory element as described.Nevertheless, because of its low resistance property, its inclusion aspart of the memory cell structure between isolation device 25 and memoryelement 30 is utilized in this embodiment.

FIG. 4 shows the structure of FIG. 3 after the introduction of maskingmaterial 180. As will become clear later, masking material 180 serves,in one sense, as an etch stop for a subsequent etch operation. FIG. 5schematically shows memory cell regions 135A and 135B in an xz plane.Overlying the memory cell is masking material 180. FIG. 6 shows across-sectional side view of memory cell region 135A through line B-B′of FIG. 5 (i.e., an xy perspective). In one embodiment, a suitablematerial for masking material 180 is a dielectric material such assilicon nitride (Si₃N₄).

FIG. 7 shows the structure of FIG. 6 (from an xy perspective) afterpatterning of the x-direction thickness of the memory cell material.FIG. 7 shows two memory cells 145A and 145B patterned from memory cellregion 135A (see FIG. 5). The patterning may be accomplished usingconventional techniques for etching, in this example, refractory metalsilicide and silicon material to the exclusion of masking material 180(e.g., Si₃N₄). The definition of the x-direction thickness involves, inone embodiment, an etch to conductive material 150 of the memory linestack to define memory cells 145A and 145B of memory cell region 135A.In the case of an etch, the etch proceeds through the memory line stackto, in this example, a portion of conductor or signal line material 150.A timed etch may be utilized to stop an etch at this point. Followingthe patterning, N-type dopant is introduced at the base of each trench190 to form pockets 200 having a dopant concentration on the order ofabout 10¹⁸−10²⁰ atoms/cm³ (e.g., N⁺ region) between memory cells 145Aand 145B. Pockets 200 serve, in one sense, to maintain continuity of arow line. Dielectric material 210 of, for example, silicon dioxidematerial is then introduced over the structure to a thickness on theorder of 100 Å to 50,000 Å.

FIG. 8 shows the structure of FIG. 7 after the formation of trenches 220through dielectric materials 210 and 180 to reducer material 170. Theformation of trenches 220 may be accomplished using etch patterning withan etchant(s) selective for etching dielectric material 210 and maskingmaterial 180 and not reducer material 170 (e.g., reducer 170 serving asan etch stop).

FIG. 9 shows the structure of FIG. 8 after the conformal introduction ofelectrode material 230. In one example, electrode material 230 ispolycrystalline semiconductor material such as polycrystalline silicon.Other suitable electrode material include carbon and semi-metals such astransition metals, including but not limited to titanium, tungsten,titanium nitride (TiN) and titanium aluminum nitride (TiAlN). Theintroduction is conformal in the sense that electrode material 230 isintroduced along the side walls and base of trench 220 such thatelectrode material 230 is in contact with reducer material 170. Theconformal introduction of electrode material 230 that is polycrystallinesilicon, for example, may follow conventional introduction techniquesknown to those skilled in the art, including chemical vapor deposition(CVD) techniques, to, for example, a film thickness on the order ofabout 50 to 350 angstroms according to current technology.

In the example where electrode material 230 is semiconductor materialsuch as polycrystalline silicon, following the introduction of electrodematerial 230, a dopant is introduced into the polycrystalline siliconto, in one aspect, lower the resistance of the material. In the exampleshown, a suitable dopant is a P-typed dopant such as boron introduced toa concentration on the order of about 10¹⁹ −10²⁰ atoms/cm³. In oneembodiment, the dopant is introduced at an angle such that electrodematerial 230A along a side wall of trench 220 is primarily exposed tothe dopant while electrode material 230B is exposed to little or nodopant. In this manner, the resistance of electrode material 230A may bereduced below the resistance of electrode material 230B. In the case ofpolycrystalline silicon, in one example, electrode material 230B issubstantially intrinsic silicon. In another embodiment, electrodematerial 230A is counter-doped. A first dopant introduced along aportion of electrode material 230A (again at an angle) adjacent reducermaterial 170 is of a first type (e.g., P⁺-type). A second dopantintroduced (also at an angle) over another portion of electrode material230A is of a second type (e.g., N⁺-type).

FIG. 10 shows the structure of FIG. 9 after the introduction of a dopantinto electrode material 230A. As illustrated, the electrode material230A is doped (with one dopant or counter-doped) about its length fromreducer material 170. FIG. 10 also shows the structure after theintroduction of dielectric material 250 into trenches 220 and aplanarization step that removes the horizontal component of electrodematerial 230. Suitable planarization techniques include those known tothose of skill in the art, such as chemical or chemical-mechanicalpolish (CMP) techniques.

FIG. 11 shows the structure of FIG. 10 after the optional introductionof modifying species 260 into a portion of electrode material 230A. Inone embodiment, modifying species 260 is introduced to raise the localresistance of electrode material 230A at a portion of electrode material270 defined by length, h₁. Electrode material 270 of polycrystallinesilicon and SiO₂, Si₃N₄, Si_(x)O_(y)N_(z), or SiC generally has a higherresistivity than doped polycrystalline silicon of electrode material230A. Suitable materials for modifying species also include thosematerials that are introduced (e.g., added, reacted, or combined) intoelectrode material 230A and raise the resistivity value within theelectrode (e.g., raise the local resistance near a volume of memorymaterial), and the resistivity value is also stable at hightemperatures. Such modifying species may be introduced by way ofimplantation or thermal means with, for example, a gaseous ambient.

As described above, electrode material 270 will be substantiallyadjacent to a memory material. Electrode material 270 may be selectedalso for its surface chemical composition in promoting adhesion of asubsequently introduced volume of memory material. Si₃N₄, for example,shows good adhesion properties for chalcogenide memory material. In somecases, electrode material 270 may not provide sufficiently suitableohmic contact between the electrode and the memory material for adesired application. In such cases, modifying material may be introducedinto the electrode at a depth below the exposed surface of theelectrode. In the example described, an electrode of polycrystallinesilicon may have polycrystalline silicon at the exposed surface(referring to FIG. 11) and modifying material 270 at a depth below theexposed surface but not throughout or adjacent for the exposed surface(e.g., 200-1000 Å below the exposed surface). In one example, a secondintroduction (e.g., deposition) may also be employed to follow theintroduction of electrode material 270 and locate polycrystallinesilicon adjacent the exposed surface of the electrode.

FIG. 12 shows the structure of FIG. 11 after the optional introductionof barrier materials 275 and 280. Barrier material 275 is, for example,titanium silicide (TiSi₂) introduced to a thickness on the order ofabout 100-300 Å. Barrier material 280 is, for example, titanium nitride(TiN) similarly introduced to a thickness on the order of about 25-300Å. The introduction of barrier materials 275 and 280 may be accomplishedusing techniques known to those skilled in the art.

FIG. 13 shows the structure of FIG. 12 after the introduction of memorymaterial 290. In one example, memory material 290 is a phase changematerial. In a more specific example, memory material 290 includes achalcogenide element(s). Examples of phase change memory material 290include, but are not limited to, compositions of the class oftellerium-germanium-antimony (Te_(x)Ge_(y)Sb_(z)) material. Memorymaterial 290, in one example according to current technology, isintroduced conformally over the substrate to a thickness on the order ofabout 300 to 600 Å.

Overlying memory material 290 in the structure of FIG. 13 are optionalbarrier materials 300 and 310 of, for example, titanium (Ti) andtitanium nitride (TiN), respectively. Barrier material serves, in oneaspect, to inhibit diffusion between the volume of memory material 290and second conductor or signal line material overlying the volume ofmemory material 290 (e.g., second conductor 10). Methods for theconformal introduction of barrier materials include such techniques asknown to those skill in the art, such a CVD process.

FIG. 14 shows the structure of FIG. 13 after the conformal introductionof second conductor or signal line material 315 over barrier materials300 and 310. In this example, second conductor or signal line material315 serves as an address line, a column line (e.g., column line 10 ofFIG. 1). Second conductor or signal line material 315 is, for example,an aluminum (Al) material, such as an aluminum alloy, or a tungsten (W)material. Methods for the introduction of second conductor or signalline material 315 include such techniques as known to those of skill inthe art such as a CVD process.

In one embodiment, following the introduction of second conductor orsignal line material 315 over barrier materials 300 and 310, secondconductor or signal line material 315, barrier materials 300 and 310,and memory material 290 are patterned into continuous strips. In thismanner, memory material 290 is contiguous with second conductor orsignal line material 315. According to one example, second conductor orsignal line material 315, barrier materials 300 and 310, and memorymaterial 290 are patterned into strips approximately one lithographicfeature size wide (e.g., 25 microns according to current technology) andgenerally orthogonal to first conductor or signal line material 140(e.g., column lines are orthogonal to row lines). Conventionalphotolithography techniques may be performed as known in the art toaccomplish the patterning including the introduction of a photosensitivemasking material to define a dimension of the strips of column materialand memory material (e.g., an x dimension) and etching according to themasking material with an etchant or etchants selective for etchingsecond conductor or signal line material 315 and memory material 290.

FIG. 15 shows the structure after patterning second conductor or signalline material 315, barrier materials 300 and 310, and memory material290. FIG. 16 shows a planar top view of the structure in an xz plane andillustrates second conductor or signal line material 315, barriermaterials 300 and 310, and memory material 290 patterned as continuousstrips over a portion of the substrate. The representation of secondconductor or signal line material 315 and memory material 290 ascontinuous strips represents an embodiment of a suitable patterning. Itis to be appreciated that, in certain instances, it may be desirable topattern such materials in a discontinuous manner.

FIG. 17 shows the structure of FIG. 15 after the introduction ofdielectric material 330 over second conductor or signal line material315. Dielectric material 330 is, for example, SiO₂ or other suitablematerial that surrounds second conductor or signal line material 315 andmemory material 290 to electronically isolate such structure. Followingintroduction, dielectric material 330 is planarized and a via is formedin a portion of the structure through dielectric material 330,dielectric material 210, and masking material 180 to reducer material170. The via is filled with conductive material 340 such as tungsten (W)and barrier material 350 such as a combination of titanium (Ti) andtitanium nitride (TiN). Techniques for introducing dielectric material330, forming and filling conductive vias, and planarizing are known tothose skilled in the art.

FIG. 17 also shows additional conductor or signal line material 320introduced and patterned to mirror that of first conductor or signalline material 140 (e.g., row line) formed on substrate 100. Mirrorconductor line material 320 mirrors first conductor or signal linematerial 140 and is coupled to first conductor or signal line material140 through a conductive via. By mirroring a doped semiconductor such asN-type silicon, mirror conductor line material 320 serves, in oneaspect, to reduce the resistance of conductor or signal line material140 in a memory array, such as memory array 5 illustrated in FIG. 1. Asuitable material for mirror conductor line material 320 includes analuminum (Al) material, such as an aluminum alloy, or a tungsten (W)material.

FIG. 18 shows the structure of FIG. 17 from a top side perspective view.The figure is presented without dielectric material 220 or 310 toillustrate further aspects of the presented structures. In relevantpart, FIG. 18 shows two column lines 3150A and 3150B of second conductoror signal line material 315 overlying two row lines 1400A and 1400B offirst conductor or signal line material 140. Disposed between columnlines 3150A and 3150B and row lines 1400A and 1400B is memory material290. Memory material 290 is, in this embodiment contiguous with columnlines 3150A and 3150B. Thus, FIG. 18 shows two strips of memory material290. In FIG. 18, electrodes 2300A and 2300B are coupled to a first stripof memory material 290 (and column line 3150A) and row lines 1400A and1400B. Electrodes 2300C and 2300D are coupled to a second strip ofmemory material 290 (and column line 3150B) and row lines 1400A and1400B. It is to be appreciated that, for a given matrix of row andcolumn lines there may be many electrodes coupled to a given volume ofmemory material contiguous with a column line.

In one embodiment, the electrode material (of electrodes 2300A, 2300B,2300C, and 2300D) including or not including one or both of the optionalbarrier materials 275 and 280, is “edgewise adjacent” to memory material290. That is, only an edge or a portion of an edge of the electrodematerial is adjacent to memory material 290. Substantially all of theremainder of the electrode is remote to memory material 290. Preferably,substantially all of the electrical communication between the electrodeis through an edge of the electrode or a portion of an edge. That is, itis preferable that substantially all electrical communication is throughat least a portion of an edge (i.e., an “edge portion”) of theelectrode.

As used herein the terminology “area of contact” is the portion of thesurface of an electrical contact through which the electrical contactelectrically communicates with memory material 290. As noted, in oneembodiment, substantially all electrical communication between memorymaterial 290 and an electrode occurs through all or a portion of an edgeof the electrode. Hence, the area of contact between the electrode andmemory material 290 is an edge of the electrode or a portion of an edgeof the electrode. That is, the area of contact between the electrode andmemory material 290 is an “edge portion” of the electrode. The electrodeneed not actually physically contact memory material 290. It issufficient that the electrode is in electrical communication with memorymaterial 290. The area of contact of the electrode and a volume ofmemory material, being only an edge portion (i.e., an edge or a portionof an edge) of the electrode, is thus very small and is proportional tothe thickness of the electrode.

While not wishing to be bound by theory, it is believed that dissipatingpower in the electrical contact from Joule heating adjacent to memorymaterial 290 may at least partially assist (or may even dominate) theprogramming of memory material 290. It is also believed that, for thepurposes of memory applications (e.g., storage of bits of information),only a small volume of memory material 290 adjacent the electrode isrequired. Hence, providing a phase change memory material in contactwith, for example, several electrode contact structures, and separatelyin electrical contact with individual row lines, allows several portionsof memory material 290 of the same strip to be individually anddistinctly programmed.

In one embodiment, a volume of memory material 290 is programmable bythe order of phase of the volume of memory material. Joule heating maybe used, for example, to amorphosize or crystallize a volume of memorymaterial 290 by raising such material to its melting point or to a pointbetween its glass transition temperature and its melting point,respectively. The memory material is chosen, in one example, so that itis generally an insulator in an amorphous phase and generally conductivein a crystalline phase.

In one embodiment, a strip of memory material 290 contiguous with, forexample, a column line of second conductor or signal line material 315,has a representative strip length of 200 microns with several electrodescoupled to the strip representing discrete memory devices. Typically,phase change memory material 290 that is a strip is predominantly in aconductive semi-metallic state with only a small portion of the materialimmediately surrounding the electrode area of contact undergoing a phasetransition. The volume of this phase change region generally depends onthe size of the contact and may be estimated at 100 to 200 angstromslarger than the electrode. In one embodiment, it is only necessary toinsure that the material in direct contact with the electrode changesphase in order to disconnect the conductive, phase change memorymaterial/column line from the electrode.

FIG. 19 presents a graphical representation of the programming (e.g.,setting and resetting) of a volume of phase change memory material.Referring to FIG. 1, programming memory element 15 (addressed by columnline 10 a and row line 20 a) involves, in one example, supplying avoltage to column line 10 a to introduce a current into the volume ofmemory material 30. The current causes a temperature increase at thevolume of memory material 30. Referring to FIG. 15, to amorphize avolume of memory material, the volume of memory material is heated to atemperature beyond the amorphisizing temperature, T_(M) (e.g., beyondthe melting point of the memory material). A representativeamorphosizing temperature for a Te_(x)Ge_(y)Sb_(z) material is on theorder of about 600° C. to 650° C. Once a temperature beyond T_(M) isreached, the volume of memory material is quenched or cooled rapidly (byremoving the current flow). The quenching is accomplished at a rate, t₁,that is faster than the rate at which the volume of memory material 30can crystallize so that the volume of memory material 30 retains itsamorphous state. To crystallize a volume of memory material 30, thetemperature is raised by current flow to the crystallization temperaturefor the material (representatively a temperature between the glasstransition temperature of the material and the melting point) andretained at that temperature for a sufficient time to crystallize thematerial. After such time, the volume of memory material is quenched (byremoving the current flow).

In the preceding example, the volume of memory material 30 was heated toa high temperature to amorphosize the material and reset the memoryelement (e.g., program 0). Heating the volume of memory material to alower crystallization temperature crystallizes the material and sets thememory element (e.g., program 1). It is to be appreciated that theassociation of reset and set with amorphous and crystalline material,respectively, is a convention and that at least an opposite conventionmay be adopted. It is also to be appreciated from this example that thevolume of memory material 30 need not be partially set or reset byvarying the current flow and duration through the volume of memorymaterial.

In the above description, a memory device structure was described.Comparing the structure to prior art structures it may be seen that thecellular representation of volumes of memory material is eliminated asis the via coupling of the memory material to an overlying conductor orsignal line (e.g., column line). The embodiment of the method of forminga memory device structure is thus simplified as alignment issues relatedto cellular formation and via placement may be reduced. Further, thesize constraints associated with via contact pitch may be eliminated.The proximity of the memory material and column lines also provides anestimated two-fold decrease in column line capacitance, reduced powerdissipation, and faster array time constraints. The configuration alsofrees routing channels as, for example, a metal level on an integratedcircuit need not accommodate a column line.

In the foregoing specification, the invention has been described withreference to specific exemplary embodiments thereof. It will, however,be evident that various modifications and changes may be made theretowithout departing from the broader spirit and scope of the invention.The specification and drawings are, accordingly, to be regarded in anillustrative rather than a restrictive sense.

What is claimed is:
 1. An apparatus comprising: a phase change materialdisposed between a first conductor and a second conductor over asubstrate, wherein the phase change material is substantially contiguouswith the second conductor and substantially orthogonal to the firstconductor.
 2. The apparatus of claim 1, wherein the phase changematerial is settable to one of at least two resistivity values inresponse to a current through the first conductor and the secondconductor.
 3. The apparatus of claim 1, wherein the second conductorcomprises one of aluminum and tungsten.
 4. The apparatus of claim 1,further comprising: a third conductor disposed over the substrate andcoupled to the first conductor.
 5. An apparatus comprising: a firstconductor; a second conductor over a substrate and electrically isolatedfrom the first conductor; a volume of phase change materialsubstantially orthogonal to the first conductor; and wherein the firstconductor and the second conductor are oriented orthogonally over thesubstrate and wherein a length of the second conductor is substantiallyequal to a length of the volume of phase change material.
 6. Theapparatus of claim 5, wherein the first conductor and the secondconductor are oriented orthogonally over the substrate and wherein alength of the second conductor is substantially equal to a length of thevolume of phase change material.
 7. The apparatus of claim 5, whereinthe second conductor comprises one of aluminum and tungsten.
 8. Anapparatus comprising: a first conductor; a second conductor over asubstrate and electrically isolated from the first conductor; a volumeof phase change material substantially orthogonal to the firstconductor; and a third conductor disposed over the substrate and coupledto the first conductor.
 9. An apparatus comprising: a matrix of Mconductors and N conductors over a substrate, wherein M and N are eachgreater than one; a plurality of electrodes coupled to the M conductors;and a phase change material coupled to a first conductor of the Nconductors, wherein a first electrode of the plurality of electrodes iscoupled between the phase change material and a first conductor of the Mconductors, wherein a second electrode of the plurality of electrodes iscoupled between the phase change material and a second conductor of theM conductors, and wherein a third electrode of the plurality ofelectrodes is coupled between the phase change material and a thirdconductor of the M conductors.
 10. The apparatus of claim 9, wherein thephase change material is contiguous with a length of the first conductorof the N conductors.
 11. The apparatus of claim 9, wherein the Mconductors comprise a semiconductor material, the apparatus furthercomprising a plurality of MM conductors formed over the substrate andcoupled to the M conductors through conductive vias.
 12. The apparatusof claim 1, wherein the substrate has a first portion and a secondportion and wherein the first portion of the substrate is doped with aP-type dopant at a concentration of approximately 5×10¹⁹ to 1×10²⁰ atomsper cubic centimeters (atoms/cm³) and the second portion of thesubstrate is P-type epitaxial silicon having a dopant concentration ofapproximately 1×10¹⁶ to 1×10¹⁷ atoms/cm³.
 13. The apparatus of claim 1,wherein the first conductor is N-type doped polysilicon having a dopantconcentration of approximately 1×10¹⁸ to 1×10¹⁹ atoms per cubiccentimeters (atoms/cm³).
 14. An apparatus, comprising: a phase changematerial formed between a first addressing line and a second addressingline over a substrate, wherein the phase change material issubstantially contiguous with the second addressing line and wherein thefirst addressing line is electrically isolated from the secondaddressing line by an isolation device coupled between the phase changematerial and the first addressing line, and wherein the isolation deviceis a diode coupled to the phase change material and the first addressingline.
 15. The apparatus of claim 14, wherein the first addressing linecomprises a semiconductor material and the second addressing linecomprises one of aluminum or tungsten.
 16. The apparatus of claim 14,wherein the diode is a PN diode formed of an N-type silicon portionhaving a dopant concentration of approximately 1×10¹⁷ to 1×10¹⁸ atomsper cubic centimeter and a P-type silicon portion having a dopantconcentration of approximately 1×10¹⁹ to 1×10²⁰ atoms/cm³.
 17. Theapparatus of claim 14, further comprising an electrode coupled betweenthe phase change material and the first addressing line.
 18. Anapparatus, comprising: a phase change material formed between a firstaddressing line and a second addressing line over a substrate, whereinthe phase change material is substantially contiguous with the secondaddressing line and wherein a length of the second addressing line issubstantially equal to a length of the phase change material.
 19. Theapparatus of claim 14, wherein the phase change material issubstantially orthogonal to the first addressing line.
 20. An apparatus,comprising; a phase change material formed between a first addressingline and a second addressing line, wherein the phase change material issubstantially orthogonal to the first addressing line, and wherein thelength of the phase change material is substantially equal to a lengthof the second addressing line and a width of the phase change materialis substantially equal to a width of the second addressing line.
 21. Theapparatus of claim 20, wherein a length of the phase change material issubstantially equal to a length of the second addressing line and awidth of the phase change material is substantially equal to a width ofthe second addressing line.
 22. The apparatus of claim 20, furthercomprising a third addressing line, wherein the phase change material isbetween the second addressing line and the third addressing line andwherein the second addressing line is electrically isolated from thefirst addressing line and the third addressing line.
 23. The apparatusof claim 22, wherein the first addressing line is electrically isolatedfrom the second addressing line by an isolation device coupled betweenthe phase change material and the first addressing line.
 24. Theapparatus of claim 20, wherein a top surface of the phase changematerial is substantially adjacent to a bottom surface of the secondaddressing line.